sky130_fd_sc_ls__a2bb2o
=======================

**2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__a2bb2o`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__a2bb2o
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  4 (A1_N, A2_N, B1, B2)
-  **Outputs**: 1 (X)

Symbols
-------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__a2bb2o.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__a2bb2o.pp.symbol.svg

Schematic
---------

.. figure:: sky130_fd_sc_ls__a2bb2o.schematic.svg
    :align: center

GDSII Layouts
-------------



.. figure:: sky130_fd_sc_ls__a2bb2o_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__a2bb2o_1


.. figure:: sky130_fd_sc_ls__a2bb2o_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__a2bb2o_2


.. figure:: sky130_fd_sc_ls__a2bb2o_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__a2bb2o_4