sky130_fd_sc_ms__edfxtp
=======================

**Delay flop with loopback enable, non-inverted clock, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__edfxtp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__edfxtp
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  3 (CLK, D, DE)
-  **Outputs**: 1 (Q)

Symbols
-------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__edfxtp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__edfxtp.pp.symbol.svg

Schematic
---------

.. figure:: sky130_fd_sc_ms__edfxtp.schematic.svg
    :align: center

GDSII Layouts
-------------



.. figure:: sky130_fd_sc_ms__edfxtp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__edfxtp_1