sky130_fd_sc_ms__dlclkp

Clock gate

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__dlclkp

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__dlclkp

  • Library: sky130_fd_sc_ms

  • Inputs: 2 (GATE, CLK)

  • Outputs: 1 (GCLK)

Symbols

../../../../../_images/sky130_fd_sc_ms__dlclkp.symbol.svg
../../../../../_images/sky130_fd_sc_ms__dlclkp.pp.symbol.svg

Schematic

../../../../../_images/sky130_fd_sc_ms__dlclkp.schematic.svg

GDSII Layouts

../../../../../_images/sky130_fd_sc_ms__dlclkp_1.svg

sky130_fd_sc_ms__dlclkp_1

../../../../../_images/sky130_fd_sc_ms__dlclkp_2.svg

sky130_fd_sc_ms__dlclkp_2

../../../../../_images/sky130_fd_sc_ms__dlclkp_4.svg

sky130_fd_sc_ms__dlclkp_4