sky130_fd_sc_ms__dlxtn

Delay latch, inverted enable, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__dlxtn

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__dlxtn

  • Library: sky130_fd_sc_ms

  • Inputs: 2 (D, GATE_N)

  • Outputs: 1 (Q)

Symbols

../../../../../_images/sky130_fd_sc_ms__dlxtn.symbol.svg
../../../../../_images/sky130_fd_sc_ms__dlxtn.pp.symbol.svg

Schematic

../../../../../_images/sky130_fd_sc_ms__dlxtn.schematic.svg

GDSII Layouts

../../../../../_images/sky130_fd_sc_ms__dlxtn_1.svg

sky130_fd_sc_ms__dlxtn_1

../../../../../_images/sky130_fd_sc_ms__dlxtn_2.svg

sky130_fd_sc_ms__dlxtn_2

../../../../../_images/sky130_fd_sc_ms__dlxtn_4.svg

sky130_fd_sc_ms__dlxtn_4