sky130_fd_sc_ms__ha

Half adder

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__ha

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__ha

  • Library: sky130_fd_sc_ms

  • Inputs: 2 (A, B)

  • Outputs: 2 (COUT, SUM)

Symbols

../../../../../_images/sky130_fd_sc_ms__ha.symbol.svg
../../../../../_images/sky130_fd_sc_ms__ha.pp.symbol.svg

Schematic

../../../../../_images/sky130_fd_sc_ms__ha.schematic.svg

GDSII Layouts

../../../../../_images/sky130_fd_sc_ms__ha_1.svg

sky130_fd_sc_ms__ha_1

../../../../../_images/sky130_fd_sc_ms__ha_2.svg

sky130_fd_sc_ms__ha_2

../../../../../_images/sky130_fd_sc_ms__ha_4.svg

sky130_fd_sc_ms__ha_4