sky130_fd_sc_hs - SKY130 High Speed Digital Standard Cells (SkyWater Provided)

Initial release of version (0, 0, 1).

List of cells in sky130_fd_sc_hs

Cell name	Description	Type	Verilog name
a2111o	2-input AND into first input of 4-input OR.	cell	sky130_fd_sc_hs__a2111o
a2111oi	2-input AND into first input of 4-input NOR.	cell	sky130_fd_sc_hs__a2111oi
a211o	2-input AND into first input of 3-input OR.	cell	sky130_fd_sc_hs__a211o
a211oi	2-input AND into first input of 3-input NOR.	cell	sky130_fd_sc_hs__a211oi
a21bo	2-input AND into first input of 2-input OR, 2nd input inverted.	cell	sky130_fd_sc_hs__a21bo
a21boi	2-input AND into first input of 2-input NOR, 2nd input inverted.	cell	sky130_fd_sc_hs__a21boi
a21o	2-input AND into first input of 2-input OR.	cell	sky130_fd_sc_hs__a21o
a21oi	2-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_hs__a21oi
a221o	2-input AND into first two inputs of 3-input OR.	cell	sky130_fd_sc_hs__a221o
a221oi	2-input AND into first two inputs of 3-input NOR.	cell	sky130_fd_sc_hs__a221oi
a222o	2-input AND into all inputs of 3-input OR.	cell	sky130_fd_sc_hs__a222o
a222oi	2-input AND into all inputs of 3-input NOR.	cell	sky130_fd_sc_hs__a222oi
a22o	2-input AND into both inputs of 2-input OR.	cell	sky130_fd_sc_hs__a22o
a22oi	2-input AND into both inputs of 2-input NOR.	cell	sky130_fd_sc_hs__a22oi
a2bb2o	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_hs__a2bb2o
a2bb2oi	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_hs__a2bb2oi
a311o	3-input AND into first input of 3-input OR.	cell	sky130_fd_sc_hs__a311o
a311oi	3-input AND into first input of 3-input NOR.	cell	sky130_fd_sc_hs__a311oi
a31o	3-input AND into first input of 2-input OR.	cell	sky130_fd_sc_hs__a31o
a31oi	3-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_hs__a31oi
a32o	3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_hs__a32o
a32oi	3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_hs__a32oi
a41o	4-input AND into first input of 2-input OR.	cell	sky130_fd_sc_hs__a41o
a41oi	4-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_hs__a41oi
and2	2-input AND.	cell	sky130_fd_sc_hs__and2
and2b	2-input AND, first input inverted.	cell	sky130_fd_sc_hs__and2b
and3	3-input AND.	cell	sky130_fd_sc_hs__and3
and3b	3-input AND, first input inverted.	cell	sky130_fd_sc_hs__and3b
and4	4-input AND.	cell	sky130_fd_sc_hs__and4
and4b	4-input AND, first input inverted.	cell	sky130_fd_sc_hs__and4b
and4bb	4-input AND, first two inputs inverted.	cell	sky130_fd_sc_hs__and4bb
buf	Buffer.	cell	sky130_fd_sc_hs__buf
bufbuf	Double buffer.	cell	sky130_fd_sc_hs__bufbuf
bufinv	Buffer followed by inverter.	cell	sky130_fd_sc_hs__bufinv
clkbuf	Clock tree buffer.	cell	sky130_fd_sc_hs__clkbuf
clkdlyinv3sd1	Clock Delay Inverter 3-stage 0.15um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv3sd1
clkdlyinv3sd2	Clock Delay Inverter 3-stage 0.25um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv3sd2
clkdlyinv3sd3	Clock Delay Inverter 3-stage 0.50um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv3sd3
clkdlyinv5sd1	Clock Delay Inverter 5-stage 0.15um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv5sd1
clkdlyinv5sd2	Clock Delay Inverter 5-stage 0.25um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv5sd2
clkdlyinv5sd3	Clock Delay Inverter 5-stage 0.50um length inner stage gate.	cell	sky130_fd_sc_hs__clkdlyinv5sd3
clkinv	Clock tree inverter.	cell	sky130_fd_sc_hs__clkinv
conb	Constant value, low, high outputs.	cell	sky130_fd_sc_hs__conb
decap	Decoupling capacitance filler.	cell	sky130_fd_sc_hs__decap
dfbbn	Delay flop, inverted set, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__dfbbn
dfbbp	Delay flop, inverted set, inverted reset, complementary outputs.	cell	sky130_fd_sc_hs__dfbbp
dfrbp	Delay flop, inverted reset, complementary outputs.	cell	sky130_fd_sc_hs__dfrbp
dfrtn	Delay flop, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__dfrtn
dfrtp	Delay flop, inverted reset, single output.	cell	sky130_fd_sc_hs__dfrtp
dfsbp	Delay flop, inverted set, complementary outputs.	cell	sky130_fd_sc_hs__dfsbp
dfstp	Delay flop, inverted set, single output.	cell	sky130_fd_sc_hs__dfstp
dfxbp	Delay flop, complementary outputs.	cell	sky130_fd_sc_hs__dfxbp
dfxtp	Delay flop, single output.	cell	sky130_fd_sc_hs__dfxtp
diode	Antenna tie-down diode.	cell	sky130_fd_sc_hs__diode
dlclkp	Clock gate.	cell	sky130_fd_sc_hs__dlclkp
dlrbn	Delay latch, inverted reset, inverted enable, complementary outputs.	cell	sky130_fd_sc_hs__dlrbn
dlrbp	Delay latch, inverted reset, non-inverted enable, complementary outputs.	cell	sky130_fd_sc_hs__dlrbp
dlrtn	Delay latch, inverted reset, inverted enable, single output.	cell	sky130_fd_sc_hs__dlrtn
dlrtp	Delay latch, inverted reset, non-inverted enable, single output.	cell	sky130_fd_sc_hs__dlrtp
dlxbn	Delay latch, inverted enable, complementary outputs.	cell	sky130_fd_sc_hs__dlxbn
dlxbp	Delay latch, non-inverted enable, complementary outputs.	cell	sky130_fd_sc_hs__dlxbp
dlxtn	Delay latch, inverted enable, single output.	cell	sky130_fd_sc_hs__dlxtn
dlxtp	Delay latch, non-inverted enable, single output.	cell	sky130_fd_sc_hs__dlxtp
dlygate4sd1	Delay Buffer 4-stage 0.15um length inner stage gates.	cell	sky130_fd_sc_hs__dlygate4sd1
dlygate4sd2	Delay Buffer 4-stage 0.18um length inner stage gates.	cell	sky130_fd_sc_hs__dlygate4sd2
dlygate4sd3	Delay Buffer 4-stage 0.50um length inner stage gates.	cell	sky130_fd_sc_hs__dlygate4sd3
dlymetal6s2s	6-inverter delay with output from 2nd stage on horizontal route.	cell	sky130_fd_sc_hs__dlymetal6s2s
dlymetal6s4s	6-inverter delay with output from 4th inverter on horizontal route.	cell	sky130_fd_sc_hs__dlymetal6s4s
dlymetal6s6s	6-inverter delay with output from 6th inverter on horizontal route.	cell	sky130_fd_sc_hs__dlymetal6s6s
ebufn	Tri-state buffer, negative enable.	cell	sky130_fd_sc_hs__ebufn
edfxbp	Delay flop with loopback enable, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__edfxbp
edfxtp	Delay flop with loopback enable, non-inverted clock, single output.	cell	sky130_fd_sc_hs__edfxtp
einvn	Tri-state inverter, negative enable.	cell	sky130_fd_sc_hs__einvn
einvp	Tri-state inverter, positive enable.	cell	sky130_fd_sc_hs__einvp
fa	Full adder.	cell	sky130_fd_sc_hs__fa
fah	Full adder.	cell	sky130_fd_sc_hs__fah
fahcin	Full adder, inverted carry in.	cell	sky130_fd_sc_hs__fahcin
fahcon	Full adder, inverted carry in, inverted carry out.	cell	sky130_fd_sc_hs__fahcon
fill	Fill cell.	cell	sky130_fd_sc_hs__fill
fill_diode	Fill diode.	cell	sky130_fd_sc_hs__fill_diode
ha	Half adder.	cell	sky130_fd_sc_hs__ha
inv	Inverter.	cell	sky130_fd_sc_hs__inv
maj3	3-input majority vote.	cell	sky130_fd_sc_hs__maj3
mux2	2-input multiplexer.	cell	sky130_fd_sc_hs__mux2
mux2i	2-input multiplexer, output inverted.	cell	sky130_fd_sc_hs__mux2i
mux4	4-input multiplexer.	cell	sky130_fd_sc_hs__mux4
nand2	2-input NAND.	cell	sky130_fd_sc_hs__nand2
nand2b	2-input NAND, first input inverted.	cell	sky130_fd_sc_hs__nand2b
nand3	3-input NAND.	cell	sky130_fd_sc_hs__nand3
nand3b	3-input NAND, first input inverted.	cell	sky130_fd_sc_hs__nand3b
nand4	4-input NAND.	cell	sky130_fd_sc_hs__nand4
nand4b	4-input NAND, first input inverted.	cell	sky130_fd_sc_hs__nand4b
nand4bb	4-input NAND, first two inputs inverted.	cell	sky130_fd_sc_hs__nand4bb
nor2	2-input NOR.	cell	sky130_fd_sc_hs__nor2
nor2b	2-input NOR, first input inverted.	cell	sky130_fd_sc_hs__nor2b
nor3	3-input NOR.	cell	sky130_fd_sc_hs__nor3
nor3b	3-input NOR, first input inverted.	cell	sky130_fd_sc_hs__nor3b
nor4	4-input NOR.	cell	sky130_fd_sc_hs__nor4
nor4b	4-input NOR, first input inverted.	cell	sky130_fd_sc_hs__nor4b
nor4bb	4-input NOR, first two inputs inverted.	cell	sky130_fd_sc_hs__nor4bb
o2111a	2-input OR into first input of 4-input AND.	cell	sky130_fd_sc_hs__o2111a
o2111ai	2-input OR into first input of 4-input NAND.	cell	sky130_fd_sc_hs__o2111ai
o211a	2-input OR into first input of 3-input AND.	cell	sky130_fd_sc_hs__o211a
o211ai	2-input OR into first input of 3-input NAND.	cell	sky130_fd_sc_hs__o211ai
o21a	2-input OR into first input of 2-input AND.	cell	sky130_fd_sc_hs__o21a
o21ai	2-input OR into first input of 2-input NAND.	cell	sky130_fd_sc_hs__o21ai
o21ba	2-input OR into first input of 2-input AND, 2nd input inverted.	cell	sky130_fd_sc_hs__o21ba
o21bai	2-input OR into first input of 2-input NAND, 2nd iput inverted.	cell	sky130_fd_sc_hs__o21bai
o221a	2-input OR into first two inputs of 3-input AND.	cell	sky130_fd_sc_hs__o221a
o221ai	2-input OR into first two inputs of 3-input NAND.	cell	sky130_fd_sc_hs__o221ai
o22a	2-input OR into both inputs of 2-input AND.	cell	sky130_fd_sc_hs__o22a
o22ai	2-input OR into both inputs of 2-input NAND.	cell	sky130_fd_sc_hs__o22ai
o2bb2a	2-input NAND and 2-input OR into 2-input AND.	cell	sky130_fd_sc_hs__o2bb2a
o2bb2ai	2-input NAND and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_hs__o2bb2ai
o311a	3-input OR into 3-input AND.	cell	sky130_fd_sc_hs__o311a
o311ai	3-input OR into 3-input NAND.	cell	sky130_fd_sc_hs__o311ai
o31a	3-input OR into 2-input AND.	cell	sky130_fd_sc_hs__o31a
o31ai	3-input OR into 2-input NAND.	cell	sky130_fd_sc_hs__o31ai
o32a	3-input OR and 2-input OR into 2-input AND.	cell	sky130_fd_sc_hs__o32a
o32ai	3-input OR and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_hs__o32ai
o41a	4-input OR into 2-input AND.	cell	sky130_fd_sc_hs__o41a
o41ai	4-input OR into 2-input NAND.	cell	sky130_fd_sc_hs__o41ai
or2	2-input OR.	cell	sky130_fd_sc_hs__or2
or2b	2-input OR, first input inverted.	cell	sky130_fd_sc_hs__or2b
or3	3-input OR.	cell	sky130_fd_sc_hs__or3
or3b	3-input OR, first input inverted.	cell	sky130_fd_sc_hs__or3b
or4	4-input OR.	cell	sky130_fd_sc_hs__or4
or4b	4-input OR, first input inverted.	cell	sky130_fd_sc_hs__or4b
or4bb	4-input OR, first two inputs inverted.	cell	sky130_fd_sc_hs__or4bb
sdfbbn	Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sdfbbn
sdfbbp	Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sdfbbp
sdfrbp	Scan delay flop, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sdfrbp
sdfrtn	Scan delay flop, inverted reset, inverted clock, single output.	cell	sky130_fd_sc_hs__sdfrtn
sdfrtp	Scan delay flop, inverted reset, non-inverted clock, single output.	cell	sky130_fd_sc_hs__sdfrtp
sdfsbp	Scan delay flop, inverted set, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sdfsbp
sdfstp	Scan delay flop, inverted set, non-inverted clock, single output.	cell	sky130_fd_sc_hs__sdfstp
sdfxbp	Scan delay flop, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sdfxbp
sdfxtp	Scan delay flop, non-inverted clock, single output.	cell	sky130_fd_sc_hs__sdfxtp
sdlclkp	Scan gated clock.	cell	sky130_fd_sc_hs__sdlclkp
sedfxbp	Scan delay flop, data enable, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hs__sedfxbp
sedfxtp	Scan delay flop, data enable, non-inverted clock, single output.	cell	sky130_fd_sc_hs__sedfxtp
tap	Tap cell with no tap connections (no contacts on metal1).	cell	sky130_fd_sc_hs__tap
tapmet1	Tap cell with isolated power and ground connections.	cell	sky130_fd_sc_hs__tapmet1
tapvgnd	Tap cell with tap to ground, isolated power connection 1 row down.	cell	sky130_fd_sc_hs__tapvgnd
tapvgnd2	Tap cell with tap to ground, isolated power connection 2 rows down.	cell	sky130_fd_sc_hs__tapvgnd2
tapvpwrvgnd	Substrate and well tap cell.	cell	sky130_fd_sc_hs__tapvpwrvgnd
xnor2	2-input exclusive NOR.	cell	sky130_fd_sc_hs__xnor2
xnor3	3-input exclusive NOR.	cell	sky130_fd_sc_hs__xnor3
xor2	2-input exclusive OR.	cell	sky130_fd_sc_hs__xor2
xor3	3-input exclusive OR.	cell	sky130_fd_sc_hs__xor3
udp_dff$NR_pp$PKG$s	Negative edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s
udp_dff$NR_pp$PKG$sN	Negative edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN
udp_dff$NSR_pp$PG	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins.	primitive	sky130_fd_sc_hs__udp_dff$NSR_pp$PG
udp_dff$NSR_pp$PG$N	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins and notifier pin.	primitive	sky130_fd_sc_hs__udp_dff$NSR_pp$PG$N
udp_dff$P_pp$PG	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$P_pp$PG
udp_dff$P_pp$PG$N	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$P_pp$PG$N
udp_dff$P_pp$PKG$s	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$P_pp$PKG$s
udp_dff$P_pp$PKG$sN	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$P_pp$PKG$sN
udp_dff$P_pp$sN	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$P_pp$sN
udp_dff$PE_pp$PG	Positive edge triggered enabled D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$PE_pp$PG
udp_dff$PE_pp$PG$N	Positive edge triggered enabled D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hs__udp_dff$PE_pp$PG$N
udp_dff$PR_pp$PG	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PR_pp$PG
udp_dff$PR_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PR_pp$PG$N
udp_dff$PR_pp$PKG$s	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PR_pp$PKG$s
udp_dff$PR_pp$PKG$sN	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PR_pp$PKG$sN
udp_dff$PR_pp$sN	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PR_pp$sN
udp_dff$PS_pp$PG	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PS_pp$PG
udp_dff$PS_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PS_pp$PG$N
udp_dff$PS_pp$PKG$s	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PS_pp$PKG$s
udp_dff$PS_pp$PKG$sN	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PS_pp$PKG$sN
udp_dff$PS_pp$sN	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hs__udp_dff$PS_pp$sN
udp_dlatch$P_pp$PG	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$P_pp$PG
udp_dlatch$P_pp$PG$N	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N
udp_dlatch$P_pp$PKG$s	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$s
udp_dlatch$P_pp$PKG$sN	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$sN
udp_dlatch$P_pp$sN	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$P_pp$sN
udp_dlatch$PR_pp$PG	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$PR_pp$PG
udp_dlatch$PR_pp$PG$N	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$PR_pp$PG$N
udp_dlatch$PR_pp$PKG$s	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s
udp_dlatch$PR_pp$PKG$sN	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$sN
udp_dlatch$PR_pp$sN	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hs__udp_dlatch$PR_pp$sN
udp_dlatch$PSa_pp$PKG$s	Positive level sensitive D-type -latch with active low	primitive	sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$s
udp_dlatch$PSa_pp$PKG$sN	Positive level sensitive D-type -latch with active low	primitive	sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$sN
udp_dlatch$PSa_pp$sN	Positive level sensitive D-type -latch with active low	primitive	sky130_fd_sc_hs__udp_dlatch$PSa_pp$sN
udp_isolatch_pp$PKG$s	Power isolating latch. Includes VPWR, KAPWR, and VGND power pins with active low sleep pin (SLEEP_B).	primitive	sky130_fd_sc_hs__udp_isolatch_pp$PKG$s
udp_isolatch_pp$PKG$sN	Power isolating latch. Includes VPWR, KAPWR, and VGND power pins with notifier and active low sleep pin (SLEEP_B).	primitive	sky130_fd_sc_hs__udp_isolatch_pp$PKG$sN
udp_mux_2to1	Two to one multiplexer	primitive	sky130_fd_sc_hs__udp_mux_2to1
udp_mux_2to1_N	Two to one multiplexer with inverting output	primitive	sky130_fd_sc_hs__udp_mux_2to1_N
udp_mux_4to2	Four to one multiplexer with 2 select controls	primitive	sky130_fd_sc_hs__udp_mux_4to2
udp_pwrgood_pp$PG	UDP_OUT :=x when VPWR!=1 or VGND!=0 UDP_OUT :=UDP_IN when VPWR==1 and VGND==0	primitive	sky130_fd_sc_hs__udp_pwrgood_pp$PG