sky130_fd_sc_hdll - SKY130 High Density Low Leakage Digital Standard Cells (SkyWater Provided)

Initial release of version (0, 1, 1).

List of cells in sky130_fd_sc_hdll

Cell name	Description	Type	Verilog name
a211o	2-input AND into first input of 3-input OR.	cell	sky130_fd_sc_hdll__a211o
a211oi	2-input AND into first input of 3-input NOR.	cell	sky130_fd_sc_hdll__a211oi
a21bo	2-input AND into first input of 2-input OR, 2nd input inverted.	cell	sky130_fd_sc_hdll__a21bo
a21boi	2-input AND into first input of 2-input NOR, 2nd input inverted.	cell	sky130_fd_sc_hdll__a21boi
a21o	2-input AND into first input of 2-input OR.	cell	sky130_fd_sc_hdll__a21o
a21oi	2-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_hdll__a21oi
a221oi	2-input AND into first two inputs of 3-input NOR.	cell	sky130_fd_sc_hdll__a221oi
a222oi	2-input AND into all inputs of 3-input NOR.	cell	sky130_fd_sc_hdll__a222oi
a22o	2-input AND into both inputs of 2-input OR.	cell	sky130_fd_sc_hdll__a22o
a22oi	2-input AND into both inputs of 2-input NOR.	cell	sky130_fd_sc_hdll__a22oi
a2bb2o	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_hdll__a2bb2o
a2bb2oi	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_hdll__a2bb2oi
a31o	3-input AND into first input of 2-input OR.	cell	sky130_fd_sc_hdll__a31o
a31oi	3-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_hdll__a31oi
a32o	3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_hdll__a32o
a32oi	3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_hdll__a32oi
and2	2-input AND.	cell	sky130_fd_sc_hdll__and2
and2b	2-input AND, first input inverted.	cell	sky130_fd_sc_hdll__and2b
and3	3-input AND.	cell	sky130_fd_sc_hdll__and3
and3b	3-input AND, first input inverted.	cell	sky130_fd_sc_hdll__and3b
and4	4-input AND.	cell	sky130_fd_sc_hdll__and4
and4b	4-input AND, first input inverted.	cell	sky130_fd_sc_hdll__and4b
and4bb	4-input AND, first two inputs inverted.	cell	sky130_fd_sc_hdll__and4bb
buf	Buffer.	cell	sky130_fd_sc_hdll__buf
bufbuf	Double buffer.	cell	sky130_fd_sc_hdll__bufbuf
bufinv	Buffer followed by inverter.	cell	sky130_fd_sc_hdll__bufinv
clkbuf	Clock tree buffer.	cell	sky130_fd_sc_hdll__clkbuf
clkinv	Clock tree inverter.	cell	sky130_fd_sc_hdll__clkinv
clkinvlp	Lower power Clock tree inverter.	cell	sky130_fd_sc_hdll__clkinvlp
clkmux2	Clock mux.	cell	sky130_fd_sc_hdll__clkmux2
conb	Constant value, low, high outputs.	cell	sky130_fd_sc_hdll__conb
decap	Decoupling capacitance filler.	cell	sky130_fd_sc_hdll__decap
dfrtp	Delay flop, inverted reset, single output.	cell	sky130_fd_sc_hdll__dfrtp
dfstp	Delay flop, inverted set, single output.	cell	sky130_fd_sc_hdll__dfstp
diode	Antenna tie-down diode.	cell	sky130_fd_sc_hdll__diode
dlrtn	Delay latch, inverted reset, inverted enable, single output.	cell	sky130_fd_sc_hdll__dlrtn
dlrtp	Delay latch, inverted reset, non-inverted enable, single output.	cell	sky130_fd_sc_hdll__dlrtp
dlxtn	Delay latch, inverted enable, single output.	cell	sky130_fd_sc_hdll__dlxtn
dlygate4sd1	Delay Buffer 4-stage 0.15um length inner stage gates.	cell	sky130_fd_sc_hdll__dlygate4sd1
dlygate4sd2	Delay Buffer 4-stage 0.18um length inner stage gates.	cell	sky130_fd_sc_hdll__dlygate4sd2
dlygate4sd3	Delay Buffer 4-stage 0.50um length inner stage gates.	cell	sky130_fd_sc_hdll__dlygate4sd3
ebufn	Tri-state buffer, negative enable.	cell	sky130_fd_sc_hdll__ebufn
einvn	Tri-state inverter, negative enable.	cell	sky130_fd_sc_hdll__einvn
einvp	Tri-state inverter, positive enable.	cell	sky130_fd_sc_hdll__einvp
fill	Fill cell.	cell	sky130_fd_sc_hdll__fill
inputiso0n	Input isolator with inverted enable.	cell	sky130_fd_sc_hdll__inputiso0n
inputiso0p	Input isolator with non-inverted enable.	cell	sky130_fd_sc_hdll__inputiso0p
inputiso1n	Input isolation, inverted sleep.	cell	sky130_fd_sc_hdll__inputiso1n
inputiso1p	Input isolation, noninverted sleep.	cell	sky130_fd_sc_hdll__inputiso1p
inv	Inverter.	cell	sky130_fd_sc_hdll__inv
isobufsrc	Input isolation, noninverted sleep.	cell	sky130_fd_sc_hdll__isobufsrc
mux2	2-input multiplexer.	cell	sky130_fd_sc_hdll__mux2
mux2i	2-input multiplexer, output inverted.	cell	sky130_fd_sc_hdll__mux2i
muxb16to1	Buffered 16-input multiplexer.	cell	sky130_fd_sc_hdll__muxb16to1
muxb4to1	Buffered 4-input multiplexer.	cell	sky130_fd_sc_hdll__muxb4to1
muxb8to1	Buffered 8-input multiplexer.	cell	sky130_fd_sc_hdll__muxb8to1
nand2	2-input NAND.	cell	sky130_fd_sc_hdll__nand2
nand2b	2-input NAND, first input inverted.	cell	sky130_fd_sc_hdll__nand2b
nand3	3-input NAND.	cell	sky130_fd_sc_hdll__nand3
nand3b	3-input NAND, first input inverted.	cell	sky130_fd_sc_hdll__nand3b
nand4	4-input NAND.	cell	sky130_fd_sc_hdll__nand4
nand4b	4-input NAND, first input inverted.	cell	sky130_fd_sc_hdll__nand4b
nand4bb	4-input NAND, first two inputs inverted.	cell	sky130_fd_sc_hdll__nand4bb
nor2	2-input NOR.	cell	sky130_fd_sc_hdll__nor2
nor2b	2-input NOR, first input inverted.	cell	sky130_fd_sc_hdll__nor2b
nor3	3-input NOR.	cell	sky130_fd_sc_hdll__nor3
nor3b	3-input NOR, first input inverted.	cell	sky130_fd_sc_hdll__nor3b
nor4	4-input NOR.	cell	sky130_fd_sc_hdll__nor4
nor4b	4-input NOR, first input inverted.	cell	sky130_fd_sc_hdll__nor4b
nor4bb	4-input NOR, first two inputs inverted.	cell	sky130_fd_sc_hdll__nor4bb
o211a	2-input OR into first input of 3-input AND.	cell	sky130_fd_sc_hdll__o211a
o211ai	2-input OR into first input of 3-input NAND.	cell	sky130_fd_sc_hdll__o211ai
o21a	2-input OR into first input of 2-input AND.	cell	sky130_fd_sc_hdll__o21a
o21ai	2-input OR into first input of 2-input NAND.	cell	sky130_fd_sc_hdll__o21ai
o21ba	2-input OR into first input of 2-input AND, 2nd input inverted.	cell	sky130_fd_sc_hdll__o21ba
o21bai	2-input OR into first input of 2-input NAND, 2nd iput inverted.	cell	sky130_fd_sc_hdll__o21bai
o221a	2-input OR into first two inputs of 3-input AND.	cell	sky130_fd_sc_hdll__o221a
o221ai	2-input OR into first two inputs of 3-input NAND.	cell	sky130_fd_sc_hdll__o221ai
o22a	2-input OR into both inputs of 2-input AND.	cell	sky130_fd_sc_hdll__o22a
o22ai	2-input OR into both inputs of 2-input NAND.	cell	sky130_fd_sc_hdll__o22ai
o2bb2a	2-input NAND and 2-input OR into 2-input AND.	cell	sky130_fd_sc_hdll__o2bb2a
o2bb2ai	2-input NAND and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_hdll__o2bb2ai
o31ai	3-input OR into 2-input NAND.	cell	sky130_fd_sc_hdll__o31ai
o32ai	3-input OR and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_hdll__o32ai
or2	2-input OR.	cell	sky130_fd_sc_hdll__or2
or2b	2-input OR, first input inverted.	cell	sky130_fd_sc_hdll__or2b
or3	3-input OR.	cell	sky130_fd_sc_hdll__or3
or3b	3-input OR, first input inverted.	cell	sky130_fd_sc_hdll__or3b
or4	4-input OR.	cell	sky130_fd_sc_hdll__or4
or4b	4-input OR, first input inverted.	cell	sky130_fd_sc_hdll__or4b
or4bb	4-input OR, first two inputs inverted.	cell	sky130_fd_sc_hdll__or4bb
probe_p	Virtual voltage probe point.	cell	sky130_fd_sc_hdll__probe_p
probec_p	Virtual current probe point.	cell	sky130_fd_sc_hdll__probec_p
sdfbbp	Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hdll__sdfbbp
sdfrbp	Scan delay flop, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hdll__sdfrbp
sdfrtn	Scan delay flop, inverted reset, inverted clock, single output.	cell	sky130_fd_sc_hdll__sdfrtn
sdfrtp	Scan delay flop, inverted reset, non-inverted clock, single output.	cell	sky130_fd_sc_hdll__sdfrtp
sdfsbp	Scan delay flop, inverted set, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hdll__sdfsbp
sdfstp	Scan delay flop, inverted set, non-inverted clock, single output.	cell	sky130_fd_sc_hdll__sdfstp
sdfxbp	Scan delay flop, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hdll__sdfxbp
sdfxtp	Scan delay flop, non-inverted clock, single output.	cell	sky130_fd_sc_hdll__sdfxtp
sdlclkp	Scan gated clock.	cell	sky130_fd_sc_hdll__sdlclkp
sedfxbp	Scan delay flop, data enable, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_hdll__sedfxbp
tap	Tap cell with no tap connections (no contacts on metal1).	cell	sky130_fd_sc_hdll__tap
tapvgnd	Tap cell with tap to ground, isolated power connection 1 row down.	cell	sky130_fd_sc_hdll__tapvgnd
tapvgnd2	Tap cell with tap to ground, isolated power connection 2 rows down.	cell	sky130_fd_sc_hdll__tapvgnd2
tapvpwrvgnd	Substrate and well tap cell.	cell	sky130_fd_sc_hdll__tapvpwrvgnd
xnor2	2-input exclusive NOR.	cell	sky130_fd_sc_hdll__xnor2
xnor3	3-input exclusive NOR.	cell	sky130_fd_sc_hdll__xnor3
xor2	2-input exclusive OR.	cell	sky130_fd_sc_hdll__xor2
xor3	3-input exclusive OR.	cell	sky130_fd_sc_hdll__xor3
udp_dff$NSR	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate).	primitive	sky130_fd_sc_hdll__udp_dff$NSR
udp_dff$NSR_pp$PG$N	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins and notifier pin.	primitive	sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N
udp_dff$P	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hdll__udp_dff$P
udp_dff$P_pp$PG$N	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_hdll__udp_dff$P_pp$PG$N
udp_dff$PR	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hdll__udp_dff$PR
udp_dff$PR_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N
udp_dff$PS	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hdll__udp_dff$PS
udp_dff$PS_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N
udp_dlatch$P	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hdll__udp_dlatch$P
udp_dlatch$P_pp$PG$N	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N
udp_dlatch$PR	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hdll__udp_dlatch$PR
udp_dlatch$PR_pp$PG$N	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N
udp_mux_2to1	Two to one multiplexer	primitive	sky130_fd_sc_hdll__udp_mux_2to1
udp_mux_2to1_N	Two to one multiplexer with inverting output	primitive	sky130_fd_sc_hdll__udp_mux_2to1_N
udp_mux_4to2	Four to one multiplexer with 2 select controls	primitive	sky130_fd_sc_hdll__udp_mux_4to2
udp_pwrgood_pp$G	UDP_OUT :=x when VPWR!=1 UDP_OUT :=UDP_IN when VPWR==1	primitive	sky130_fd_sc_hdll__udp_pwrgood_pp$G
udp_pwrgood_pp$P	UDP_OUT :=x when VPWR!=1 UDP_OUT :=UDP_IN when VPWR==1	primitive	sky130_fd_sc_hdll__udp_pwrgood_pp$P
udp_pwrgood_pp$PG	UDP_OUT :=x when VPWR!=1 or VGND!=0 UDP_OUT :=UDP_IN when VPWR==1 and VGND==0	primitive	sky130_fd_sc_hdll__udp_pwrgood_pp$PG
udp_pwrgood_pp$PG$S	UDP_OUT :=x when VPWR!=1 or VGND!=0 UDP_OUT :=UDP_IN when VPWR==1 and VGND==0	primitive	sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S