sky130_fd_sc_ms - SKY130 Medium Speed Digital Standard Cells (SkyWater Provided)

Initial release of version (0, 0, 1).

List of cells in sky130_fd_sc_ms

Cell name	Description	Type	Verilog name
a2111o	2-input AND into first input of 4-input OR.	cell	sky130_fd_sc_ms__a2111o
a2111oi	2-input AND into first input of 4-input NOR.	cell	sky130_fd_sc_ms__a2111oi
a211o	2-input AND into first input of 3-input OR.	cell	sky130_fd_sc_ms__a211o
a211oi	2-input AND into first input of 3-input NOR.	cell	sky130_fd_sc_ms__a211oi
a21bo	2-input AND into first input of 2-input OR, 2nd input inverted.	cell	sky130_fd_sc_ms__a21bo
a21boi	2-input AND into first input of 2-input NOR, 2nd input inverted.	cell	sky130_fd_sc_ms__a21boi
a21o	2-input AND into first input of 2-input OR.	cell	sky130_fd_sc_ms__a21o
a21oi	2-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_ms__a21oi
a221o	2-input AND into first two inputs of 3-input OR.	cell	sky130_fd_sc_ms__a221o
a221oi	2-input AND into first two inputs of 3-input NOR.	cell	sky130_fd_sc_ms__a221oi
a222o	2-input AND into all inputs of 3-input OR.	cell	sky130_fd_sc_ms__a222o
a222oi	2-input AND into all inputs of 3-input NOR.	cell	sky130_fd_sc_ms__a222oi
a22o	2-input AND into both inputs of 2-input OR.	cell	sky130_fd_sc_ms__a22o
a22oi	2-input AND into both inputs of 2-input NOR.	cell	sky130_fd_sc_ms__a22oi
a2bb2o	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_ms__a2bb2o
a2bb2oi	2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_ms__a2bb2oi
a311o	3-input AND into first input of 3-input OR.	cell	sky130_fd_sc_ms__a311o
a311oi	3-input AND into first input of 3-input NOR.	cell	sky130_fd_sc_ms__a311oi
a31o	3-input AND into first input of 2-input OR.	cell	sky130_fd_sc_ms__a31o
a31oi	3-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_ms__a31oi
a32o	3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.	cell	sky130_fd_sc_ms__a32o
a32oi	3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.	cell	sky130_fd_sc_ms__a32oi
a41o	4-input AND into first input of 2-input OR.	cell	sky130_fd_sc_ms__a41o
a41oi	4-input AND into first input of 2-input NOR.	cell	sky130_fd_sc_ms__a41oi
and2	2-input AND.	cell	sky130_fd_sc_ms__and2
and2b	2-input AND, first input inverted.	cell	sky130_fd_sc_ms__and2b
and3	3-input AND.	cell	sky130_fd_sc_ms__and3
and3b	3-input AND, first input inverted.	cell	sky130_fd_sc_ms__and3b
and4	4-input AND.	cell	sky130_fd_sc_ms__and4
and4b	4-input AND, first input inverted.	cell	sky130_fd_sc_ms__and4b
and4bb	4-input AND, first two inputs inverted.	cell	sky130_fd_sc_ms__and4bb
buf	Buffer.	cell	sky130_fd_sc_ms__buf
bufbuf	Double buffer.	cell	sky130_fd_sc_ms__bufbuf
bufinv	Buffer followed by inverter.	cell	sky130_fd_sc_ms__bufinv
clkbuf	Clock tree buffer.	cell	sky130_fd_sc_ms__clkbuf
clkdlyinv3sd1	Clock Delay Inverter 3-stage 0.15um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv3sd1
clkdlyinv3sd2	Clock Delay Inverter 3-stage 0.25um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv3sd2
clkdlyinv3sd3	Clock Delay Inverter 3-stage 0.50um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv3sd3
clkdlyinv5sd1	Clock Delay Inverter 5-stage 0.15um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv5sd1
clkdlyinv5sd2	Clock Delay Inverter 5-stage 0.25um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv5sd2
clkdlyinv5sd3	Clock Delay Inverter 5-stage 0.50um length inner stage gate.	cell	sky130_fd_sc_ms__clkdlyinv5sd3
clkinv	Clock tree inverter.	cell	sky130_fd_sc_ms__clkinv
conb	Constant value, low, high outputs.	cell	sky130_fd_sc_ms__conb
decap	Decoupling capacitance filler.	cell	sky130_fd_sc_ms__decap
dfbbn	Delay flop, inverted set, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__dfbbn
dfbbp	Delay flop, inverted set, inverted reset, complementary outputs.	cell	sky130_fd_sc_ms__dfbbp
dfrbp	Delay flop, inverted reset, complementary outputs.	cell	sky130_fd_sc_ms__dfrbp
dfrtn	Delay flop, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__dfrtn
dfrtp	Delay flop, inverted reset, single output.	cell	sky130_fd_sc_ms__dfrtp
dfsbp	Delay flop, inverted set, complementary outputs.	cell	sky130_fd_sc_ms__dfsbp
dfstp	Delay flop, inverted set, single output.	cell	sky130_fd_sc_ms__dfstp
dfxbp	Delay flop, complementary outputs.	cell	sky130_fd_sc_ms__dfxbp
dfxtp	Delay flop, single output.	cell	sky130_fd_sc_ms__dfxtp
diode	Antenna tie-down diode.	cell	sky130_fd_sc_ms__diode
dlclkp	Clock gate.	cell	sky130_fd_sc_ms__dlclkp
dlrbn	Delay latch, inverted reset, inverted enable, complementary outputs.	cell	sky130_fd_sc_ms__dlrbn
dlrbp	Delay latch, inverted reset, non-inverted enable, complementary outputs.	cell	sky130_fd_sc_ms__dlrbp
dlrtn	Delay latch, inverted reset, inverted enable, single output.	cell	sky130_fd_sc_ms__dlrtn
dlrtp	Delay latch, inverted reset, non-inverted enable, single output.	cell	sky130_fd_sc_ms__dlrtp
dlxbn	Delay latch, inverted enable, complementary outputs.	cell	sky130_fd_sc_ms__dlxbn
dlxbp	Delay latch, non-inverted enable, complementary outputs.	cell	sky130_fd_sc_ms__dlxbp
dlxtn	Delay latch, inverted enable, single output.	cell	sky130_fd_sc_ms__dlxtn
dlxtp	Delay latch, non-inverted enable, single output.	cell	sky130_fd_sc_ms__dlxtp
dlygate4sd1	Delay Buffer 4-stage 0.15um length inner stage gates.	cell	sky130_fd_sc_ms__dlygate4sd1
dlygate4sd2	Delay Buffer 4-stage 0.18um length inner stage gates.	cell	sky130_fd_sc_ms__dlygate4sd2
dlygate4sd3	Delay Buffer 4-stage 0.50um length inner stage gates.	cell	sky130_fd_sc_ms__dlygate4sd3
dlymetal6s2s	6-inverter delay with output from 2nd stage on horizontal route.	cell	sky130_fd_sc_ms__dlymetal6s2s
dlymetal6s4s	6-inverter delay with output from 4th inverter on horizontal route.	cell	sky130_fd_sc_ms__dlymetal6s4s
dlymetal6s6s	6-inverter delay with output from 6th inverter on horizontal route.	cell	sky130_fd_sc_ms__dlymetal6s6s
ebufn	Tri-state buffer, negative enable.	cell	sky130_fd_sc_ms__ebufn
edfxbp	Delay flop with loopback enable, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__edfxbp
edfxtp	Delay flop with loopback enable, non-inverted clock, single output.	cell	sky130_fd_sc_ms__edfxtp
einvn	Tri-state inverter, negative enable.	cell	sky130_fd_sc_ms__einvn
einvp	Tri-state inverter, positive enable.	cell	sky130_fd_sc_ms__einvp
fa	Full adder.	cell	sky130_fd_sc_ms__fa
fah	Full adder.	cell	sky130_fd_sc_ms__fah
fahcin	Full adder, inverted carry in.	cell	sky130_fd_sc_ms__fahcin
fahcon	Full adder, inverted carry in, inverted carry out.	cell	sky130_fd_sc_ms__fahcon
fill	Fill cell.	cell	sky130_fd_sc_ms__fill
fill_diode	Fill diode.	cell	sky130_fd_sc_ms__fill_diode
ha	Half adder.	cell	sky130_fd_sc_ms__ha
inv	Inverter.	cell	sky130_fd_sc_ms__inv
maj3	3-input majority vote.	cell	sky130_fd_sc_ms__maj3
mux2	2-input multiplexer.	cell	sky130_fd_sc_ms__mux2
mux2i	2-input multiplexer, output inverted.	cell	sky130_fd_sc_ms__mux2i
mux4	4-input multiplexer.	cell	sky130_fd_sc_ms__mux4
nand2	2-input NAND.	cell	sky130_fd_sc_ms__nand2
nand2b	2-input NAND, first input inverted.	cell	sky130_fd_sc_ms__nand2b
nand3	3-input NAND.	cell	sky130_fd_sc_ms__nand3
nand3b	3-input NAND, first input inverted.	cell	sky130_fd_sc_ms__nand3b
nand4	4-input NAND.	cell	sky130_fd_sc_ms__nand4
nand4b	4-input NAND, first input inverted.	cell	sky130_fd_sc_ms__nand4b
nand4bb	4-input NAND, first two inputs inverted.	cell	sky130_fd_sc_ms__nand4bb
nor2	2-input NOR.	cell	sky130_fd_sc_ms__nor2
nor2b	2-input NOR, first input inverted.	cell	sky130_fd_sc_ms__nor2b
nor3	3-input NOR.	cell	sky130_fd_sc_ms__nor3
nor3b	3-input NOR, first input inverted.	cell	sky130_fd_sc_ms__nor3b
nor4	4-input NOR.	cell	sky130_fd_sc_ms__nor4
nor4b	4-input NOR, first input inverted.	cell	sky130_fd_sc_ms__nor4b
nor4bb	4-input NOR, first two inputs inverted.	cell	sky130_fd_sc_ms__nor4bb
o2111a	2-input OR into first input of 4-input AND.	cell	sky130_fd_sc_ms__o2111a
o2111ai	2-input OR into first input of 4-input NAND.	cell	sky130_fd_sc_ms__o2111ai
o211a	2-input OR into first input of 3-input AND.	cell	sky130_fd_sc_ms__o211a
o211ai	2-input OR into first input of 3-input NAND.	cell	sky130_fd_sc_ms__o211ai
o21a	2-input OR into first input of 2-input AND.	cell	sky130_fd_sc_ms__o21a
o21ai	2-input OR into first input of 2-input NAND.	cell	sky130_fd_sc_ms__o21ai
o21ba	2-input OR into first input of 2-input AND, 2nd input inverted.	cell	sky130_fd_sc_ms__o21ba
o21bai	2-input OR into first input of 2-input NAND, 2nd iput inverted.	cell	sky130_fd_sc_ms__o21bai
o221a	2-input OR into first two inputs of 3-input AND.	cell	sky130_fd_sc_ms__o221a
o221ai	2-input OR into first two inputs of 3-input NAND.	cell	sky130_fd_sc_ms__o221ai
o22a	2-input OR into both inputs of 2-input AND.	cell	sky130_fd_sc_ms__o22a
o22ai	2-input OR into both inputs of 2-input NAND.	cell	sky130_fd_sc_ms__o22ai
o2bb2a	2-input NAND and 2-input OR into 2-input AND.	cell	sky130_fd_sc_ms__o2bb2a
o2bb2ai	2-input NAND and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_ms__o2bb2ai
o311a	3-input OR into 3-input AND.	cell	sky130_fd_sc_ms__o311a
o311ai	3-input OR into 3-input NAND.	cell	sky130_fd_sc_ms__o311ai
o31a	3-input OR into 2-input AND.	cell	sky130_fd_sc_ms__o31a
o31ai	3-input OR into 2-input NAND.	cell	sky130_fd_sc_ms__o31ai
o32a	3-input OR and 2-input OR into 2-input AND.	cell	sky130_fd_sc_ms__o32a
o32ai	3-input OR and 2-input OR into 2-input NAND.	cell	sky130_fd_sc_ms__o32ai
o41a	4-input OR into 2-input AND.	cell	sky130_fd_sc_ms__o41a
o41ai	4-input OR into 2-input NAND.	cell	sky130_fd_sc_ms__o41ai
or2	2-input OR.	cell	sky130_fd_sc_ms__or2
or2b	2-input OR, first input inverted.	cell	sky130_fd_sc_ms__or2b
or3	3-input OR.	cell	sky130_fd_sc_ms__or3
or3b	3-input OR, first input inverted.	cell	sky130_fd_sc_ms__or3b
or4	4-input OR.	cell	sky130_fd_sc_ms__or4
or4b	4-input OR, first input inverted.	cell	sky130_fd_sc_ms__or4b
or4bb	4-input OR, first two inputs inverted.	cell	sky130_fd_sc_ms__or4bb
sdfbbn	Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sdfbbn
sdfbbp	Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sdfbbp
sdfrbp	Scan delay flop, inverted reset, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sdfrbp
sdfrtn	Scan delay flop, inverted reset, inverted clock, single output.	cell	sky130_fd_sc_ms__sdfrtn
sdfrtp	Scan delay flop, inverted reset, non-inverted clock, single output.	cell	sky130_fd_sc_ms__sdfrtp
sdfsbp	Scan delay flop, inverted set, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sdfsbp
sdfstp	Scan delay flop, inverted set, non-inverted clock, single output.	cell	sky130_fd_sc_ms__sdfstp
sdfxbp	Scan delay flop, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sdfxbp
sdfxtp	Scan delay flop, non-inverted clock, single output.	cell	sky130_fd_sc_ms__sdfxtp
sdlclkp	Scan gated clock.	cell	sky130_fd_sc_ms__sdlclkp
sedfxbp	Scan delay flop, data enable, non-inverted clock, complementary outputs.	cell	sky130_fd_sc_ms__sedfxbp
sedfxtp	Scan delay flop, data enable, non-inverted clock, single output.	cell	sky130_fd_sc_ms__sedfxtp
tap	Tap cell with no tap connections (no contacts on metal1).	cell	sky130_fd_sc_ms__tap
tapmet1	Tap cell with isolated power and ground connections.	cell	sky130_fd_sc_ms__tapmet1
tapvgnd	Tap cell with tap to ground, isolated power connection 1 row down.	cell	sky130_fd_sc_ms__tapvgnd
tapvgnd2	Tap cell with tap to ground, isolated power connection 2 rows down.	cell	sky130_fd_sc_ms__tapvgnd2
tapvpwrvgnd	Substrate and well tap cell.	cell	sky130_fd_sc_ms__tapvpwrvgnd
xnor2	2-input exclusive NOR.	cell	sky130_fd_sc_ms__xnor2
xnor3	3-input exclusive NOR.	cell	sky130_fd_sc_ms__xnor3
xor2	2-input exclusive OR.	cell	sky130_fd_sc_ms__xor2
xor3	3-input exclusive OR.	cell	sky130_fd_sc_ms__xor3
udp_dff$NSR	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate).	primitive	sky130_fd_sc_ms__udp_dff$NSR
udp_dff$NSR_pp$PG$N	Negative edge triggered D flip-flop (Q output UDP) with both active high reset and set (set dominate). Includes VPWR and VGND power pins and notifier pin.	primitive	sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N
udp_dff$P	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_ms__udp_dff$P
udp_dff$P_pp$PG$N	Positive edge triggered D flip-flop (Q output UDP).	primitive	sky130_fd_sc_ms__udp_dff$P_pp$PG$N
udp_dff$PR	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_ms__udp_dff$PR
udp_dff$PR_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_ms__udp_dff$PR_pp$PG$N
udp_dff$PS	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_ms__udp_dff$PS
udp_dff$PS_pp$PG$N	Positive edge triggered D flip-flop with active high	primitive	sky130_fd_sc_ms__udp_dff$PS_pp$PG$N
udp_dlatch$P	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_ms__udp_dlatch$P
udp_dlatch$P_pp$PG$N	D-latch, gated standard drive / active high (Q output UDP)	primitive	sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N
udp_dlatch$PR	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_ms__udp_dlatch$PR
udp_dlatch$PR_pp$PG$N	D-latch, gated clear direct / gate active high (Q output UDP)	primitive	sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N
udp_mux_2to1	Two to one multiplexer	primitive	sky130_fd_sc_ms__udp_mux_2to1
udp_mux_2to1_N	Two to one multiplexer with inverting output	primitive	sky130_fd_sc_ms__udp_mux_2to1_N
udp_mux_4to2	Four to one multiplexer with 2 select controls	primitive	sky130_fd_sc_ms__udp_mux_4to2
udp_pwrgood_pp$G	UDP_OUT :=x when VPWR!=1 UDP_OUT :=UDP_IN when VPWR==1	primitive	sky130_fd_sc_ms__udp_pwrgood_pp$G
udp_pwrgood_pp$P	UDP_OUT :=x when VPWR!=1 UDP_OUT :=UDP_IN when VPWR==1	primitive	sky130_fd_sc_ms__udp_pwrgood_pp$P
udp_pwrgood_pp$PG	UDP_OUT :=x when VPWR!=1 or VGND!=0 UDP_OUT :=UDP_IN when VPWR==1 and VGND==0	primitive	sky130_fd_sc_ms__udp_pwrgood_pp$PG